Your cart is empty.

Cart
Lists
Public lists Fiction value enginering Jatin View all
Your lists Log in to create your own lists

Log in to your account
Your cookies
Search history

opac header image

Home
e-books
e-library

Search the catalog by:

Search the catalog by keyword

Advanced search
Authority search
Tag cloud
Library

Log in to your account

Card number or username: Password:

Home
ISBD view for VHDL for logic synthesis

Normal view MARC view ISBD view

VHDL for logic synthesis

Rushton, Andrew

VHDL for logic synthesis - 2nd - John Wiley 2001 - 375

Standard No.: 109895

Dewey Class. No.: 621.392 / RUS

VHDL for logic synthesis

APA

Rushton A., . (2001). VHDL for logic synthesis. : John Wiley.

Chicago

Rushton Andrew, . 2001. VHDL for logic synthesis. : John Wiley.

Harvard

Rushton A., . (2001). VHDL for logic synthesis. : John Wiley.

MLA

Rushton Andrew, . VHDL for logic synthesis. : John Wiley. 2001.

Place hold
Print
Cite
Add to your cart (remove)
Save record
BIBTEX Dublin Core MARCXML MARC (non-Unicode/MARC-8) MARC (Unicode/UTF-8) MARC (Unicode/UTF-8, Standard) MODS (XML) RIS ISBD
More searches

Search for this title in:
Other Libraries (WorldCat) Other Databases (Google Scholar) Online Stores (Bookfinder.com) Open Library (openlibrary.org)

Exporting to Dublin Core...

Simple DC-RDF

OAI-DC

SRW-DC

Copyright © 2023 JC Bose University of Science & Technology, YMCA.

Powered by Koha

Powered by Koha